Still lower noise radio astronomy (was: low-noise amplifiers for radio astronomy )

wrote:

In the meantime try plotting a graph of SNR versus load
resistance for a given source resistance. Remember for
a given bandwidth, the noise power is independent of
the resistance hence noise voltage varies as the sqrt of
the resistance.

I am not sure that I see the point of this exercise.

The noise generated in a reasonably designed amp is primarily due to
transistor noise.
Even if it was due to the amplifier's input resistance (i.e. the load
seen by the source), this makes no difference. The device supresses
amplifier noise, period.

Now to the question of the source. Assuming it absorbs all incident
energy, the signal power is V^2 / R . The signal voltage is thus sqrt
(incident power x R). However, if the noise voltage is also
proportional to sqrt R, the source resistance makes no difference to
s/n ratio.

The same happens if you perform the corresponding calculation for
signal current and noise current.

If we ignore e.g. transmission line reflections due to mismatching
then, whatever that source resistance, the signal voltage at the
amplifier input is obviously maximised when that load resistance is
infinite. Conversely, the signal current is maximised when that load
resistance is zero.

If we don't ignore e.g. transmission line reflections due to
mismatching, then this becomes your field not mine. We both know that
maximum power transfer is achieved when the source resistance and load
resistance are equal. However, I am not so sure that this rule can
still be relied on at the two limiting cases where (a) we are driving
an idealised amplifier input stage which only amplifies voltage
(without requiring any current), and (b) we are driving an idealised
amplifier input stage which only amplifies current (without requiring
any voltage).

Perhaps you could tell me the answers, in those two limiting cases.

(If you want to switch to email for this, that is fine by me too)
John Bell
(Change John to Liberty to bypass anti-spam email filter)

"John (Liberty) Bell" wrote in message
...
wrote:

In the meantime try plotting a graph of SNR versus load
resistance for a given source resistance. Remember for
a given bandwidth, the noise power is independent of
the resistance hence noise voltage varies as the sqrt of
the resistance.

I am not sure that I see the point of this exercise.

The noise generated in a reasonably designed amp is primarily due to
transistor noise.

Obviously if you could only suppress the input resistance
thermal noise then internal sources become more important,
but since they are thermal too I am assuming your method
would work equally well on both. Whatever the transistor
noise, minimising that due to the input resistance remains
desirable and since we aren't discussing your technique,
I am restricting myself to the question of matching since
that can be resolved.

Even if it was due to the amplifier's input resistance (i.e. the load
seen by the source), this makes no difference. The device supresses
amplifier noise, period.

Cool ;-)

Now to the question of the source. Assuming it absorbs all incident
energy, the signal power is V^2 / R . The signal voltage is thus sqrt
(incident power x R). However, if the noise voltage is also
proportional to sqrt R, the source resistance makes no difference to
s/n ratio.

The same happens if you perform the corresponding calculation for
signal current and noise current.

If we ignore e.g. transmission line reflections due to mismatching
then, whatever that source resistance, the signal voltage at the
amplifier input is obviously maximised when that load resistance is
infinite. Conversely, the signal current is maximised when that load
resistance is zero.

If we don't ignore e.g. transmission line reflections due to
mismatching, then this becomes your field not mine. We both know that
maximum power transfer is achieved when the source resistance and load
resistance are equal. However, I am not so sure that this rule can
still be relied on at the two limiting cases where (a) we are driving
an idealised amplifier input stage which only amplifies voltage
(without requiring any current), ...

Ok, let's go into this in more detail. Consider a signal
source of voltage Vs and impedance Rs which is fed to an
amplifier giving an output Vo. For a high impedance design
using a fet or HEMT, we can model the amp as a perfect
voltage amplifier with a parallel input resistance:

Amp
(Vs)--[Rs]--*--|-- Vo
|
[Rp]
|
=== Gnd

By putting a transformer in front of the real amp (not
shown), we can make the actual resistance look like any
value for Rp we choose, so what is the best Rp?

First consider Rp Rs. The current from the load is

Is = Vs / (Rs+Rp) ~ Vs/Rp

so the operation is almost constant current. The input
signal voltage is

Vs = Is.Rp

The noise power is given by

Pn = k.T.B

where k is Boltzmann's constant, T is the temperature in
Kelvins and B is the bandwidth in Hz. The power in a
resistor in general is

P = V^2/R

hence the voltage is

V = sqrt(P.R)

The noise voltage is therefore

Vn = sqrt(Pn.Rp) = sqrt(k.T.B.Rp)

For Rp Rs, as we vary Rp the signal voltage varies
in proportion while the noise voltage varies as the
square root. That means if we quadruple Rp, the signal
voltage will increase by a factor of four while the
noise voltage only doubles hence increasing Rp will
improve the SNR.

Now consider Rp Rs. The current from the load is

Is = Vs / (Rs+Rp) ~ Vs/Rs

so the operation is almost independent of Rp. The
noise voltage is still is proportional to the square
root of Rp so now any increase in Rp has no effect
on the signal voltage presented to the amp but does
increase the noise.

For Rp Rs, we can improve the SNR by decreasing Rp.
Put those two together and clearly there will be a
maximum of SNR somewhere between Rp Rs and Rp Rs
and it turns out that maximum occurs at Rp = Rs.

... and (b) we are driving an idealised
amplifier input stage which only amplifies current (without requiring
any voltage).

Perhaps you could tell me the answers, in those two limiting cases.

This case is more complex.

V Amp
(Is)--*--[Rs]--|-- Io
| \
[Rp] \
| \
=== Gnd Virtual earth

Now we have a current source in parallel with Rp.
The amp is controlled by current into the virtual
earth point and it produces a proportional output
current Io. Power in a resistor is I^2.R but in
this case the noise power in Rs is dissipated
in both Rs and Rp (the noise looks like a current
mode generator across Rs). Alternatively the noise
current in resistor Rs is

In = sqrt(Pn/Rs)

For the case Rs Rp, the situation is simple.
Almost all of the signal current enters the amp so
it is independent of Rs but the noise is mostly
dissipated in Rs hence as Rs is reduced the noise
current increases as the inverse square root and
the SNR gets poorer.

For Rs Rp therefore we can improve SNR by
increasing Rs.

For Rs Rp, the thermal noise from Rs is mostly
dissipated in Rp as is the signal current Is. The
voltage V therefore is substantially independent
of Rs for both noise and signal and the SNR tends
towards the ratio of the source power to the noise
power in Rs asymptotically. The resulting conclusion
is that the higher Rs the better. In other words, if
you have a 50 ohm source, the best series resistor
in front of your current-input amp is many megohms!

Clearly this isn't right. What I think is missing
from this picture is that the output current has to
be changed back to a voltage to be useful by feeding
Io into a resistor. It needs to be proportional to Rs
for a given gain and the noise from that resistor
will then increase as Rs increases producing an
optimal value for Rs.

That raises the question of whether such an amp fed
into a current-input DAC but give the best noise
performance but in transistor amps, the base spreading
resistance creates a practical limit and we were
talking about HEMT amps anyway.

George

[Mod. note: entire quoted thread removed -- mjh]

I apologize in advance, but I haven't taken the time to read this
entire thread. So hopefully I won't repeat something already
discussed.

Why approach this problem from the point-of-view of currents and
voltages? Why not use S-parameters?

Also, for the LNAs that I'm aware of, there is no resitance in the
first-stage matching network. Just conductive and inductive
impedances.

The key is to match the input matching network to the optimal noise
match of the first-stage transistor. The trade-off is that this tends
to hurt input return losses of the amp, but luckily some inductive
feedback will fix that. So, basically you have
Noise Figure = Minimum Noise Figure of Transistor + (terms related to
impedance matching)

Regards

OK I am switching this particular part of the discussion between me and
George to private email now. It is clear that each of us has different
areas of specialised expertise, and I think further progress should be
more rapid if that part of the discussion is now continued in private.


Regards

John Bell

Peritas wrote:
[Mod. note: entire quoted thread removed -- mjh]

I apologize in advance, but I haven't taken the time to read this
entire thread. So hopefully I won't repeat something already
discussed.

Why approach this problem from the point-of-view of currents and
voltages? Why not use S-parameters?

Also, for the LNAs that I'm aware of, there is no resitance in the
first-stage matching network. Just conductive and inductive
impedances.

Quite. What we started discussing, before simplifying matters, was the
internal capacitance of the transistor gate, the resistance to which
that connects internally, and the desirability of achieving impedance
matching of that with the source impedance. The reason we switched to
discussing pure resistances was that George pointed out that correct
choice of inductors would cancel out capacitance at the designed centre
frequency, thus leaving pure resistances to worry about for impedance
matching.

The key is to match the input matching network to the optimal noise
match of the first-stage transistor. The trade-off is that this tends
to hurt input return losses of the amp, but luckily some inductive
feedback will fix that.

This raises an interesting point that I was wondering about. If we
consider, for simplicity, the idealised situation where the input
transistor is replaced by an op amp, then the ratio of negative
feedback Z / souce Z, not only defines the gain, but also reduces the
effective input resistence at the inverting amplifier terminal to zero
(virtual earth). How does that consequence of negative feedback affect
the impedance balancing we have been discussing?

John

Peritas wrote:
[Mod. note: entire quoted thread removed -- mjh]

I apologize in advance, but I haven't taken the time to read this
entire thread. So hopefully I won't repeat something already
discussed.

Why approach this problem from the point-of-view of currents and
voltages? Why not use S-parameters?

S-parameters typically assume the input and output
ports are terminated in matched loads while we are
discussing the loading to optimise the SNR for a given
source impedance. S-parameters also don't address
the question of thermal noise directly.

Also, for the LNAs that I'm aware of, there is no resitance in the
first-stage matching network. Just conductive and inductive
impedances.

In my experience, those components are arranged to
cancel the reactive part of the active component input
impedance to leave a resistive load.

The key is to match the input matching network to the optimal noise
match of the first-stage transistor. The trade-off is that this tends
to hurt input return losses of the amp, but luckily some inductive
feedback will fix that. So, basically you have
Noise Figure = Minimum Noise Figure of Transistor + (terms related to
impedance matching)

Yes, that is conventional (for good reasons) but the
question John is asking is whether, if we are prepared
to tolerate a high value of S11, we can get a small
improvement in SNR when considering only the limiting
thermal noise in the real part of the input impedance.

best regards
George

John (Liberty) Bell wrote:
OK I am switching this particular part of the discussion between me and
George to private email now. ...

I am discussiing the topic with John by email but I
thought these two papers may be of wider interest
as an indication of the level of detail that current
"state of the art" work considers (or at least the
state a few years ago). While our discussion has
been mainly at a theoretical level, real world
limitations of component manufacture is a prime
driver of the amplifier design.

http://www.imec.be/esscirc/esscirc20...gs/data/76.pdf

The following also discusses "themal noise canceling"
though perhaps not in the sense that John means:

http://amsacta.cib.unibo.it/archive/...1/GA043200.PDF

George

wrote:
John (Liberty) Bell wrote:
OK I am switching this particular part of the discussion between me and
George to private email now. ...

I am discussiing the topic with John by email but I
thought these two papers may be of wider interest
as an indication of the level of detail that current
"state of the art" work considers (or at least the
state a few years ago). While our discussion has
been mainly at a theoretical level, real world
limitations of component manufacture is a prime
driver of the amplifier design.

http://www.imec.be/esscirc/esscirc20...gs/data/76.pdf

The following also discusses "themal noise canceling"
though perhaps not in the sense that John means:

http://amsacta.cib.unibo.it/archive/...1/GA043200.PDF

George

Although these papers were both interesting and potentially relevant in
their own right, there are several additional points I think worth
mentioning.

In specific relation to
http://amsacta.cib.unibo.it/archive/...1/GA043200.PDF, although
the authors claim to be describing a CMOS LNA in the abstract, it turns
out in the paper that they have only described NMOS and bipolar in
practice.

For those who don't understand the difference (which appears to include
these authors), a CMOS amplifier (or digital switch) stage comprises
the conductive channels of an n type and a p type MOSFET connected in
series (typically across the power rails), whilst their respective
gates are connected in parallel, such that when one is switched on, the
other is switched off, with a mutually conductive (approximately
linear) region there between.

Having said that, I note, more importantly, from section C of this
paper:
A) That impedance matching and noise minimisation are indeed not the
same thing, as I suggested in a recent response from me to George.
B) That negative feedback can and has been employed to break this
trade-off (as I already had in mind [as fine detailing] within a
practical implementation of my design)
C) That global negative feedback will indeed change Zin, as I suggested
was also an important consideration in my response to Peritas.

Finally I can confirm that George was correct in guessing that these
papers have nothing to do with my central noise suppression proposal.
Nevertheless, I cannot currently see why such methods could not be used
in conjunction with that proposal, if desired.


John Bell
(Change John to Liberty to bypass anti-spam email filter)

John (Liberty) Bell wrote:
Peritas wrote:
[Mod. note: entire quoted thread removed -- mjh]

I apologize in advance, but I haven't taken the time to read this
entire thread. So hopefully I won't repeat something already
discussed.

Why approach this problem from the point-of-view of currents and
voltages? Why not use S-parameters?

Also, for the LNAs that I'm aware of, there is no resitance in the
first-stage matching network. Just conductive and inductive
impedances.

Quite. What we started discussing, before simplifying matters, was the
internal capacitance of the transistor gate, the resistance to which
that connects internally, and the desirability of achieving impedance
matching of that with the source impedance. The reason we switched to
discussing pure resistances was that George pointed out that correct
choice of inductors would cancel out capacitance at the designed centre
frequency, thus leaving pure resistances to worry about for impedance
matching.

Well, from my point-of-view, this is how I think of the initial steps
to designing an LNA. (Incidentally, I think this post will address
some of George's comments that he made independently in response to my
"s-parameter" post mentioned above.)

1. Obtain an s-parameter model and noise model for the FET that you
plan to use. You can then take this info and use it to plot the
optimal input return loss (IRL) match of the FET and the optimal noise
match of the FET on a Smith chart. All of the internal resistances,
inductances, and capacitances of the FET are included in this
information.

2. For an LNA, one starts with the input stage matching network. You
know that there will be a 50ohm load connected to the input of the
entire amp (unless a different load is spec'd), and by this point, you
know what load you need to present to the 1st stage FET to get a good
IRL and a good noise figure. Now, the first problem is that the
optimal IRL match will not be the optimal noise match. In many cases,
a shunt inductor hanging off the FET's source pads is used to pull
these two points closer together on the Smith chart.

3. At this point, one can start using capacitors and inductors to match
the outside 50ohm load to the IRL/Noise load(s) of the FET (which are
now closer together, but still not on top of each other).

4. Of course, one must consider stability, gain, and whatever else is
spec'd by the end-user. Also, once one adds stages after the 1st stage
FET, some of steps 1-3 will need to be re-tweaked b/c the FET's
isolation is not infinite. Oh, and one does not want to through away
gain in the first stage. The noise contribution of subsequent stages
is reduced by the amount of gain in the first stage!


The key is to match the input matching network to the optimal noise
match of the first-stage transistor. The trade-off is that this tends
to hurt input return losses of the amp, but luckily some inductive
feedback will fix that.

This raises an interesting point that I was wondering about. If we
consider, for simplicity, the idealised situation where the input
transistor is replaced by an op amp, then the ratio of negative
feedback Z / souce Z, not only defines the gain, but also reduces the
effective input resistence at the inverting amplifier terminal to zero
(virtual earth). How does that consequence of negative feedback affect
the impedance balancing we have been discussing?

John

I'm not sure how to answer this question specifically, but does step #2
help by analogy?

Remind me now. What is the original purpose/intent of this thread?
Maybe my answers regarding LNA design are too generalized.

Regards

wrote:

[--snip--]

The key is to match the input matching network to the optimal noise
match of the first-stage transistor. The trade-off is that this tends
to hurt input return losses of the amp, but luckily some inductive
feedback will fix that. So, basically you have
Noise Figure = Minimum Noise Figure of Transistor + (terms related to
impedance matching)

Yes, that is conventional (for good reasons) but the
question John is asking is whether, if we are prepared
to tolerate a high value of S11, we can get a small
improvement in SNR when considering only the limiting
thermal noise in the real part of the input impedance.

best regards
George

Why kill S11 for a *small* improvement in SNR? (Perhaps I do need to
take the time to review this thread more closely.)