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#21
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Still lower noise radio astronomy (was: low-noise amplifiers for radio astronomy )
John (Liberty) Bell wrote:
Peritas wrote: [Mod. note: entire quoted thread removed -- mjh] I apologize in advance, but I haven't taken the time to read this entire thread. So hopefully I won't repeat something already discussed. Why approach this problem from the point-of-view of currents and voltages? Why not use S-parameters? Also, for the LNAs that I'm aware of, there is no resitance in the first-stage matching network. Just conductive and inductive impedances. Quite. What we started discussing, before simplifying matters, was the internal capacitance of the transistor gate, the resistance to which that connects internally, and the desirability of achieving impedance matching of that with the source impedance. The reason we switched to discussing pure resistances was that George pointed out that correct choice of inductors would cancel out capacitance at the designed centre frequency, thus leaving pure resistances to worry about for impedance matching. Well, from my point-of-view, this is how I think of the initial steps to designing an LNA. (Incidentally, I think this post will address some of George's comments that he made independently in response to my "s-parameter" post mentioned above.) 1. Obtain an s-parameter model and noise model for the FET that you plan to use. You can then take this info and use it to plot the optimal input return loss (IRL) match of the FET and the optimal noise match of the FET on a Smith chart. All of the internal resistances, inductances, and capacitances of the FET are included in this information. 2. For an LNA, one starts with the input stage matching network. You know that there will be a 50ohm load connected to the input of the entire amp (unless a different load is spec'd), and by this point, you know what load you need to present to the 1st stage FET to get a good IRL and a good noise figure. Now, the first problem is that the optimal IRL match will not be the optimal noise match. In many cases, a shunt inductor hanging off the FET's source pads is used to pull these two points closer together on the Smith chart. 3. At this point, one can start using capacitors and inductors to match the outside 50ohm load to the IRL/Noise load(s) of the FET (which are now closer together, but still not on top of each other). 4. Of course, one must consider stability, gain, and whatever else is spec'd by the end-user. Also, once one adds stages after the 1st stage FET, some of steps 1-3 will need to be re-tweaked b/c the FET's isolation is not infinite. Oh, and one does not want to through away gain in the first stage. The noise contribution of subsequent stages is reduced by the amount of gain in the first stage! The key is to match the input matching network to the optimal noise match of the first-stage transistor. The trade-off is that this tends to hurt input return losses of the amp, but luckily some inductive feedback will fix that. This raises an interesting point that I was wondering about. If we consider, for simplicity, the idealised situation where the input transistor is replaced by an op amp, then the ratio of negative feedback Z / souce Z, not only defines the gain, but also reduces the effective input resistence at the inverting amplifier terminal to zero (virtual earth). How does that consequence of negative feedback affect the impedance balancing we have been discussing? John I'm not sure how to answer this question specifically, but does step #2 help by analogy? Remind me now. What is the original purpose/intent of this thread? Maybe my answers regarding LNA design are too generalized. Regards |
#22
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Still lower noise radio astronomy (was: low-noise amplifiers for radio astronomy )
Peritas wrote:
wrote: ..... The key is to match the input matching network to the optimal noise match of the first-stage transistor. The trade-off is that this tends to hurt input return losses of the amp, but luckily some inductive feedback will fix that. So, basically you have Noise Figure = Minimum Noise Figure of Transistor + (terms related to impedance matching) Yes, that is conventional (for good reasons) but the question John is asking is whether, if we are prepared to tolerate a high value of S11, we can get a small improvement in SNR when considering only the limiting thermal noise in the real part of the input impedance. Why kill S11 for a *small* improvement in SNR? (Perhaps I do need to take the time to review this thread more closely.) It is a theoretical question. The main topic is that John believes he has a method that can cancel out thermal noise. He has mentioned obtaining a 20dB improvement in the past so his technique would take an LNA with a noise figure of say 2dB and turn it into a -18dB. He isn't sharing the details but apparently the requirement for matching the input is of interest to him. HTH George |
#23
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Still lower noise radio astronomy (was: low-noise amplifiers for radio astronomy )
I think it is probably best to respond to these points from Peritas, in
approximately reverse order. Peritas wrote: Remind me now. What is the original purpose/intent of this thread? For me, the purpose of the thread is to facilitate my evaluation of a technique I hit upon for supressing preamplifier noise. This still appears to be radically different from anything hitherto published. Maybe my answers regarding LNA design are too generalized. More probably not. If I understand correctly, you are describing standard methods for optimising SNR which were presumably used for LNAs that are already in use. Without being particularly familiar with what those methods are, I was able to derive, from information kindly provided, that my technique could improve on such performance, by a further 20 dB or so. However, in order to ensure that I can achieve that 20 dB improvement in practice, I need to ensure that I too also employ the most appropriate of those known optimisation techniques, within the context of my own design. John (Liberty) Bell wrote: This raises an interesting point that I was wondering about. If we consider, for simplicity, the idealised situation where the input transistor is replaced by an op amp, then the ratio of negative feedback Z / souce Z, not only defines the gain, but also reduces the effective input resistance at the inverting amplifier terminal to zero (virtual earth). How does that consequence of negative feedback affect the impedance balancing we have been discussing? I'm not sure how to answer this question specifically, but does step #2 help by analogy? More informative for me were points B and C of the 4th paragraph of my posting of Tues, Sep 12 2006 5:17 pm, obtained by reading the last reference given by George. Peritas wrote separately in response to : Why kill S11 for a *small* improvement in SNR? (Perhaps I do need to take the time to review this thread more closely.) ANY available improvement in SNR is worth having in principle, because this is what defines the limit of range for intelligible processing of information. Further amplification of a signal is relatively cheap and easy. It is removal of the noise proportion near the input which is more tricky (AKA costly). (We have already established, for example, that the cryo-coolers tend to cost more than the entire electronics, within pre-existing state of the art preamp designs). Without asking and examining the foregoing and related questions, we do not know for sure how small *small* is, or whether it is worth having in practice. Regards John Bell (Change John to Liberty to bypass anti-spam email filter) |
#24
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Still lower noise radio astronomy (was: low-noise amplifiers for radio astronomy )
John (Liberty) Bell wrote:
wrote: The following also discusses "themal noise canceling" though perhaps not in the sense that John means: http://amsacta.cib.unibo.it/archive/...1/GA043200.PDF George Although these papers were both interesting and potentially relevant in their own right, there are several additional points I think worth mentioning. In specific relation to http://amsacta.cib.unibo.it/archive/...1/GA043200.PDF, although the authors claim to be describing a CMOS LNA in the abstract, it turns out in the paper that they have only described NMOS and bipolar in practice. For those who don't understand the difference (which appears to include these authors), a CMOS amplifier (or digital switch) stage comprises the conductive channels of an n type and a p type MOSFET connected in series (typically across the power rails), whilst their respective gates are connected in parallel, such that when one is switched on, the other is switched off, with a mutually conductive (approximately linear) region there between. I would like to correct myself on a minor technical point here. The defining characteristic of CMOS is a mix of n type and a p type MOSFETs which operate in a complimentary manner. If the authors have actually used any such mix of MOSFETs in their implimentation, they certainly managed to obscure that fact from the reader, by using an identical representation for every MOSFET in the paper. If so, this level of potential ambiguity for every transistor, makes their circuit diagrams extremely difficult to interpret. John Bell (Change John to Liberty to bypass anti-spam email filter) |
#25
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Still lower noise radio astronomy (was: low-noise amplifiers for radio astronomy )
Peritas wrote:
Well, from my point-of-view, this is how I think of the initial steps to designing an LNA. (Incidentally, I think this post will address some of George's comments that he made independently in response to my "s-parameter" post mentioned above.) 1. Obtain an s-parameter model and noise model for the FET that you plan to use. You can then take this info and use it to plot the optimal input return loss (IRL) match of the FET and the optimal noise match of the FET on a Smith chart. All of the internal resistances, inductances, and capacitances of the FET are included in this information. 2. For an LNA, one starts with the input stage matching network. You know that there will be a 50ohm load connected to the input of the entire amp (unless a different load is spec'd), and by this point, you know what load you need to present to the 1st stage FET to get a good IRL and a good noise figure. Now, the first problem is that the optimal IRL match will not be the optimal noise match. In many cases, a shunt inductor hanging off the FET's source pads is used to pull these two points closer together on the Smith chart. 3. At this point, one can start using capacitors and inductors to match the outside 50ohm load to the IRL/Noise load(s) of the FET (which are now closer together, but still not on top of each other). This approach sounds different to the use (at lower frequencies), of an impedance matching transformer here, or the equivalent pcb 'squiggle' suggested by George for an equivalent impedance matching at higher frequencies . That sounded like quite a neat approach to me. Or have I misunderstood precisely what is involved in George's 'squiggle'? 4. Of course, one must consider stability, gain, and whatever else is spec'd by the end-user. Also, once one adds stages after the 1st stage FET, some of steps 1-3 will need to be re-tweaked b/c the FET's isolation is not infinite. I imagine that such re-tweaking might need to be more drastic if global negative feedback is employed, unless, of course, you can factor that in from the outset. Oh, and one does not want to through away gain in the first stage. The noise contribution of subsequent stages is reduced by the amount of gain in the first stage! Generally speaking, that is one of the advantages of global negative feedback, as opposed to local negative feedback applied to the first stage. However, I noticed from http://amsacta.cib.unibo.it/archive/...1/GA043200.PDF that concern was expressed over potential instability introduced by this method. That surprised me because that problem always has to be addressed in negative feedback designs. Typically, at some frequency significantly above the design freq. of the amp, negative feedback changes to positive feedback due to phase shifts at such higher frequencies. This problem is typically solved by damping out such potentially oscillatory higher frequencies. Is there something about RF design which makes such a solution more tricky at RF frequencies? Regards John Bell (Change John to Liberty to bypass anti-spam email filter) |
#26
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Still lower noise radio astronomy (was: low-noise amplifiers for radio astronomy )
John (Liberty) Bell wrote:
wrote: snip http://www.imec.be/esscirc/esscirc20...gs/data/76.pdf The following also discusses "themal noise canceling" though perhaps not in the sense that John means: http://amsacta.cib.unibo.it/archive/...1/GA043200.PDF Although these papers were both interesting and potentially relevant in their own right, there are several additional points I think worth mentioning. In specific relation to http://amsacta.cib.unibo.it/archive/...1/GA043200.PDF, although the authors claim to be describing a CMOS LNA in the abstract, it turns out in the paper that they have only described NMOS and bipolar in practice. Actually the paper title says it is a review of noise cancelling techniques. For those who don't understand the difference (which appears to include these authors), a CMOS amplifier (or digital switch) stage comprises the conductive channels of an n type and a p type MOSFET connected in series (typically across the power rails), whilst their respective gates are connected in parallel, such that when one is switched on, the other is switched off, with a mutually conductive (approximately linear) region there between. What John says is true but in this case there is a bit of industry jargon involved. What the paper says is "A wide-band LNA according to the concept of fig. 3b was designed in a 0.25um standard CMOS process." Silicon fabs are built to maufacture a specific process and CMOS is used for the vast majority of consumer devices and is much cheaper than alternatives such as GaAs that are used in high speed work. What the article says is that the chip was built on a standard CMOS production line. Having said that, I note, more importantly, from section C of this paper: A) That impedance matching and noise minimisation are indeed not the same thing, as I suggested in a recent response from me to George. I was wrong. I missed the fact that Rs shunts Rp when calculating the noise voltage. The cosequence is that the SNR is asymptotic to a factor of 2 better than the matched condition at infinite mismatch. B) That negative feedback can and has been employed to break this trade-off (as I already had in mind [as fine detailing] within a practical implementation of my design) That was what I was really bringing to your attention as a pointer to the state of "prior art" that you have previously mentioned. C) That global negative feedback will indeed change Zin, as I suggested was also an important consideration in my response to Peritas. Finally I can confirm that George was correct in guessing that these papers have nothing to do with my central noise suppression proposal. Nevertheless, I cannot currently see why such methods could not be used in conjunction with that proposal, if desired. That was my hope, that these articles would give you a guide to the performance of a good off-the-shelf LNA that you could use as a "black box" and around which you could apply your technique. The noise figures are "2db" for CMOS or 1.53dB for bipolar in one paper and 1.8db (minimum) in the other so assuming a feasible range of 1.5dB to 2.0dB is justifiable. If your technique can achieve just 6dB cancellation of the noise but requires a mismatch causing a further 3dB signal loss, you would still end up with an overall NF better than -1dB. My question would be whether NF 0dB violates the laws of thermodynamics, but the answer isn't obvious. George |
#28
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Still lower noise radio astronomy (was: low-noise amplifiers for radio astronomy )
John (Liberty) Bell wrote:
wrote: John (Liberty) Bell wrote: (Note to readers. The second half of this response is more directly pertinent to the general topic than the specifics of technology responded to immediately below.) I'll trim a lot where it is no longer contentious. Actually the paper title says it is a review of noise cancelling techniques. Yes. What threw me was the specific claim in the abstract that the technique was applied to fabricate CMOS LNAs. On closer reading, this still appears to be untrue. What John says is true but in this case there is a bit of industry jargon involved. What the paper says is "A wide-band LNA according to the concept of fig. 3b was designed in a 0.25um standard CMOS process." Silicon fabs are built to maufacture a specific process and CMOS is used for the vast majority of consumer devices and is much cheaper than alternatives such as GaAs that are used in high speed work. Although I too was (and still am) a great enthusiast for CMOS, I think you are probably over icing the cake a little here. NMOS was, and probably still is, cheaper than CMOS since it involves both less process steps, and wafer real estate. Since many consumer products are extremely price sensitive, CMOS penetration has been less comprehensive than I would have hoped, by now. This, I suggest, is largely why a disgracefully high proportion of cheap products still infuriatingly manage to forget what they were supposed to be doing, as soon as the power is interrupted. I don't think you understand the current split. I found a list of fabs: http://www.semizone.com/fab/advance.tcl In the 'technology' box enter NMOS and you find 17 fabs. Enter CMOS and it returns 665 fabs, 97.5% of the total. The search doesn't give a total for wafers but I guess it is probably at least as high a percentage. The point is that specialist fabs like SiGe or GaAs are much more expensive. What the article says is that the chip was built on a standard CMOS production line. If so, it seems that this was just because that happened to be the production line they had convenient access to. Yes, undoubtedly. If the diagrams are anything to go by, they merely implimented NMOS technology on that production line, in practice. That's right. Either the abstract writer only skipped through the paper and didn't realise that, or the misleading sentence was inserted intentionally, in order to gain kudos from the 'hip-ness' of a production line they had only partially used, in practice. ; ) I think you are mis-reading the statement to say they "implemented a CMOS LNA" when in fact it only says they "implemented an LNA in a CMOS process". The captions on the figures say "CMOS LNA" but I read that as just shorthand. That was my hope, that these articles would give you a guide to the performance of a good off-the-shelf LNA that you could use as a "black box" and around which you could apply your technique. Quite, and thanks again. However, if we are talking specifics of actually physically building the prototype, paper 1 would definitely require access to and control of the masks on a chip production line, and paper 2 probably would too because, although not declared therein, I would guess that the noise figures quoted are dependent on a tight matching of transistors that can only be achieved by fabrication on a single chip. In one paper figure 6 is a photo of the 860um by 610um chip they made on the CMOS line: http://www.imec.be/esscirc/esscirc20...gs/data/76.pdf In the other, fig 6 shows the circuit of the 478um by 500um chip they made on a "15GHz industrial bipolar process." http://amsacta.cib.unibo.it/archive/...1/GA043200.PDF From prior experience I know that such control of a commercial production line would be prohibitively expensive for a 'DIY' proof that an inventive idea works (at the required frequencies). One therefore needs to convince the chip manufacturer that the product could earn them millions. Nope, you give them the dsign and they charge you for making it. For propotypes, there are companies that will put your sample with other peoples and do smaller quantities but it is still expensive of course. That's where simulation is needed to get you backing and/or grants. snip The noise figures are "2db" for CMOS or 1.53dB for bipolar in one paper and 1.8db (minimum) in the other so assuming a feasible range of 1.5dB to 2.0dB is justifiable. Oh dear. After having to switch from my understanding of dB to Noise Temperature, I find that we are now back to dB again (but not as I know it, Jim) More later - I have to go ..... George |
#29
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Still lower noise radio astronomy (was: low-noise amplifiers for radio astronomy )
John (Liberty) Bell wrote:
wrote: John (Liberty) Bell wrote: contd. ... The noise figures are "2db" for CMOS or 1.53dB for bipolar in one paper and 1.8db (minimum) in the other so assuming a feasible range of 1.5dB to 2.0dB is justifiable. Oh dear. After having to switch from my understanding of dB to Noise Temperature, I find that we are now back to dB again (but not as I know it, Jim) http://en.wikipedia.org/wiki/Noise_figure If my understanding is correct, dB is a relative (logarithmic) measure, http://en.wikipedia.org/wiki/Decibel the magnitude (and sign) of which depends on your choice of reference point. In contrast, dBm is defined as an absolute measure. dBm is dB relative to 1mW. An example was the Pioneer home page where it gave the AGC level as -177.62 dBm. I assume you know AGC is automatic gain control so this says the gain has adjusted to receive signal+noise at that level. http://spaceprojects.arc.nasa.gov/Sp...er/PNStat.html If your technique can achieve just 6dB cancellation of the noise but requires a mismatch causing a further 3dB signal loss, you would still end up with an overall NF better than -1dB. Quite. My question would be whether NF 0dB violates the laws of thermodynamics, but the answer isn't obvious. Very true. One of the reasons why I chose a 20 dB improvement as a target figure for the prototype was that I had already noticed, on the basis of the last reference given by Jonathan Thornburg (in the first posting), that this would bring us within a whisker of the there quoted theoretical minimum noise T ( + or -, depending on freq., within the range) Well as you can see, with a noise figure for current good practice LNA design of around 1.5dB, which is relative to the thermal noise of the input impedance, you only need 2dB to go beyond that limit, hence my scepticism regarding a 20dB claim. My opinion is that I stand a better than fighting chance of geting beyond that theoretical limit, on the basis of my own calculations. That would mean that the theory is wrong, because the theorists failed to consider the angle I am exploiting. That should suffice, hopefully, to prove to every patent examiner in the world, that the inventive step was not obvious. If you want to prove it will work, not just to others but yourself first ;-), I would strongly advise simulation. We would not consider going to even a lash-up on the bench without ding that first. A typical LNA only has a few components and you are not talking about vast complex circuitry or DSP at these frequencies so if you don't have a simulator available at work try the evaluation version of Micro-Cap: http://www.spectrum-soft.com/demoform.shtm http://www.spectrum-soft.com/index.shtm It is limited to 50 components but that should be about enough. A working sim and a non-disclosure agreement should get you into doors. George |
#30
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Still lower noise radio astronomy (was: low-noise amplifiers for radio astronomy )
wrote:
John (Liberty) Bell wrote: wrote: John (Liberty) Bell wrote: I don't think you understand the current split. I found a list of fabs: http://www.semizone.com/fab/advance.tcl In the 'technology' box enter NMOS and you find 17 fabs. Enter CMOS and it returns 665 fabs, 97.5% of the total. The search doesn't give a total for wafers but I guess it is probably at least as high a percentage. That does seem to confirm that CMOS has taken over, at least for small fabs, which is what we would be talking about. The point is that specialist fabs like SiGe or GaAs are much more expensive. I absolutely agree with you there. What the article says is that the chip was built on a standard CMOS production line. If so, it seems that this was just because that happened to be the production line they had convenient access to. Yes, undoubtedly. snip I think you are mis-reading the statement to say they "implemented a CMOS LNA" when in fact it only says they "implemented an LNA in a CMOS process". The captions on the figures say "CMOS LNA" but I read that as just shorthand. Quoting direct from the abstract they say "the technique has been applied to wideband CMOS LNAs", which sounded pretty unambiguous to me. However, I don't think we need to argue this point further as we are both in agreement over what is really going on. That was my hope, that these articles would give you a guide to the performance of a good off-the-shelf LNA that you could use as a "black box" and around which you could apply your technique. Quite, and thanks again. However, if we are talking specifics of actually physically building the prototype, paper 1 would definitely require access to and control of the masks on a chip production line, and paper 2 probably would too because, although not declared therein, I would guess that the noise figures quoted are dependent on a tight matching of transistors that can only be achieved by fabrication on a single chip. In one paper figure 6 is a photo of the 860um by 610um chip they made on the CMOS line: http://www.imec.be/esscirc/esscirc20...gs/data/76.pdf In the other, fig 6 shows the circuit of the 478um by 500um chip they made on a "15GHz industrial bipolar process." http://amsacta.cib.unibo.it/archive/...1/GA043200.PDF From prior experience I know that such control of a commercial production line would be prohibitively expensive for a 'DIY' proof that an inventive idea works (at the required frequencies). One therefore needs to convince the chip manufacturer that the product could earn them millions. Nope, you give them the design and they charge you for making it. For propotypes, there are companies that will put your sample with other peoples and do smaller quantities but it is still expensive of course. That's where simulation is needed to get you backing and/or grants. Yes, you are right. I do recall now that Electronics magazine was talking about custom fab lines where a variety of customer designs could be manufactured on a single wafer, even before I "retired". Since the device would naturally benefit from integration, this is starting to sound like one exciting possibility (dependent on what these CMOS noise figures actually mean [in terms of noise temperature], and what the cost is actually going to be.) Another potential reason why this angle could be exciting is that, once the masks have been prepared, the additional cost per chip should decrease substantially the more you make. As I already mentioned to Steve Willner, CMOS could also be a promising candidate for cryogenic cooling. With a reasonable sized yield of good room temperature chips, one might then find a smaller but still reasonable yield of cryogenic temperature functional chips, within the same batch. The same production run might therefore yield a batch of LNAs that can achieve close to liquid helium performance without cryogenic cooling, and a further (more expensive) batch that can be cooled to reduce LNA noise to virtually zero, relative to the other sources of system noise. For considering this angle in greater detail, it would be helpful to know whether FETs that fail at low temperatures do so catastrophically, or if they start working again when warmed. Does Steve Willner have any insight on this from his work with cryogenic infrared amplifiers? If not, this shouldn't be very expensive to test, for anyone who already has a crto-cooler. Regards John |
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