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#32
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![]() "Dr. O" dr.o@xxxxx wrote in message ... "budbiss" wrote in message ... Cardmanwrote: On Thu, 22 Jan 2004 20:38:04 GMT, (Gary W. Swearingen) wrote: Someone please ask the "reset" question, when if it can be made to restart, then this may solve their problem. I heard on the news this afternoon that they were going to attempt at sending some type of RESET signal to the rover. I don't remember if they said exactly when they plan to do it though. I believe it was ABCnews that reported this. Well that's a typical Microsoft Windows user talking there, hehe. A little MS bashing here? The computers on board spacecraft are designed specifically not to fail and they won't. Besides, the computer resets itself automatically if a problem crops up. Umm, so which is it. They wont' fail or they will? Most likely the computer is still working but the data modulator (sits between the computer and the radio transmitter) is faulty. But I would be surprised if they didn't have a backup for the low-gain radio, but it seems they don't. It could also be a general computer failure, which leaves the radio sending only beeps but the rover being essentially 'dead.' I thought you said the computer is designed not to fail? Make up your mind here. |
#33
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Hello,
Sorry if this all sounds conspiracy oriented, but does anyone know how many people would have to be lying if there were any lying ordered by government? Are other countries' space experts able to verify the rover data coming back, before and after this 'coma'? I'm wondering if - say the rover found something extraordinary up there, might the powers in control successfully hide that knowledge from the public and other countries? Is the data up and down link to and from the rover encrypted so that only NASA or JPL agents can control it? Also, how possible a problem is 'hacking' of said streams? How robust is that data link? Thanks, Memer |
#35
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In article ,
Sander Vesik wrote: Probably SEU, Single Event Upset, where a bit gets flipped by a particle hit on a chip. If it's an important bit, a mess can result. :-) ... Umm... you mean somebody would seriously consider having a project measured in millions of dollars and not include trivial small things like SECDED, memory scrubbing and restarts? Error-correcting memory is usual in spacecraft. But that doesn't do you any good if the flipped bit is in the *processor*. (This does, helpfully, seem to be a vastly less common case.) It's easy to add redundancy to protect memory, but doing the same for logic circuitry -- especially fast stuff -- is difficult. -- MOST launched 30 June; science observations running | Henry Spencer since Oct; first surprises seen; papers pending. | |
#36
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In article ,
Sander Vesik wrote: Probably SEU, Single Event Upset, where a bit gets flipped by a particle hit on a chip. If it's an important bit, a mess can result. :-) ... Umm... you mean somebody would seriously consider having a project measured in millions of dollars and not include trivial small things like SECDED, memory scrubbing and restarts? Error-correcting memory is usual in spacecraft. But that doesn't do you any good if the flipped bit is in the *processor*. (This does, helpfully, seem to be a vastly less common case.) It's easy to add redundancy to protect memory, but doing the same for logic circuitry -- especially fast stuff -- is difficult. -- MOST launched 30 June; science observations running | Henry Spencer since Oct; first surprises seen; papers pending. | |
#37
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(Henry Spencer) wrote in message ...
Error-correcting memory is usual in spacecraft. But that doesn't do you any good if the flipped bit is in the *processor*. (This does, helpfully, seem to be a vastly less common case.) The amount of charge in a DRAM storage cell representing a 1 is just barely different from the representation of a 0. Even a low-energy event might be enough to flip the stored bit. I suspect there are few places in a CPU, except maybe the cache, where so little energy is required to flip a bit. A flash chip probably requires a high energy event to flip a bit. If such events are sufficiently rare I'd be tempted to perhaps do no more than ECC in software for science data and redundant storage for mission variables, and dispense with exotic rad-hardening altogether (ordinary flash is deployed in the many millions, any rad-hardened part maybe in the hundreds, and the latter implies uncertain reliability to me). It's easy to add redundancy to protect memory, but doing the same for logic circuitry -- especially fast stuff -- is difficult. Years ago I read the specs on Intel's i960 part and it had a "checker mode" designed for this. Multiple CPUs could be wired together with only one driving outputs at a time. On write cycles the "slaves" would compare what the master was writing to what their own logic core would have written and would flag any difference to external hardware. Usually only one CPU was in disagreement and would therefore be voted off the island. A slave could have its outputs enabled and become a master on the fly if needed. The software could be designed to restart the processors periodically to bring stragglers back in sync. It looked straightforward to implement in a system and I assume there are modern choices for this. |
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