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SAR simulation performed at ground-based GAMS mapping
facility after data has been transmitted from on-board
the GAMS satellite using the imaging radar sensor data.
Ground-based simulators at the GAMS mapping facility
receive the transmitted data in binary format that is
eventually translated to C for image processing. The C
simulator and the utilities read and write binary files.

A sample code VHDL simulator for earth based SAR
mapping that reads and writes ASCII files is given below.
The difference between this simulator and a proposed C
simulator for GAMS is that since VHDL utilizes on-board
processing, data can be transmitted instantaneously via
fiber optic cable. However, with new broadband frequencies
such as the Ku-band opening up to duplex or TMDA (Time
Division Multiple Access), the possibilities for wireless
broadband would eliminate the need for fiber optic
transmission. Nevertheless, code is presented in the
link below for interest in developing a more useful SAR
processor for orbital based data processing from the
GAMS mapping facility:

http://home.comcast.net/~samuel_rans...or_in_VHDL.htm

At the start of the simulation, main enters a loop in
which it reads commands and data on the control/diagnostic
port. When a step or stepN command is received, and if
all of the load commands have been received, nframe is
set to 1 or N, run is set to 1 and main exits the command
reading loop. (The code must be changed here for operation
with multiple step commands in a command script.)

The image processing performed is exactly that described in
Chapter 3 (Processor Requirements). The VHDL code is
shown in abbreviated form in Figure 8 where lines starting
with '**' are descriptions of code which has been removed
for this figure. Some comment lines were also removed.

The read_pri (found in read_adts.vhd) procedure is called
for each enabled polarization in each pulse. The procedure
searches the radar data stream at the input port and
returns auxiliary data in the aux array and the range
value in rangex (if it is an HH pulse) and radar data in
the rod array.

Lats is an array of five time values which is used as
a ring buffer. When the last pulse data in a frame is
received, the current time value is inserted into the
next position in lats. This array is used in the
latency_control process to determine when data is to be
sent out from the processor.

This section of the VHDL code is a direct transliteration
of the image processing code in the sar-simd.c program.
In fact, comments were directly copied, which accounts
for the error in "--Write the second half of this range
cell to file (sic)." The cmult and crmult procedures are
defined in complex.vhd and cdft and cdfti are defined in
cdft.vhd. write_frm_hdr is defined in frm_hdr.vhd.

The image processing is done in zero simulated time but
it was desired to simulate processor latency.

Therefore, data is stored in the two fifo processes between
when it is generated and when it is to be presented at the
output port. Since the amount of required storage is
dependent on the specified latency, the fifo processes
create linked lists of buffers using VHDL access types.

Each of the two processes waits on its strobe signals which
indicate availability of a new datum to write in the buffer
or a request to read a value. The empty signals indicate to
the latency_control process that there is no data available.

The latency_control process waits until run is set, and then
waits until current time minus the time in the lats variable
for the first frame is greater than the specified latency.

When that condition is reached, it puts out header and image
data for each of the enabled polarizations. Then, if more than
one frame is being processed, the process waits until latency
time for the next frame is reached.

If more than four frames are specified in one command or if
the simulator were to be modified to run more than one step
command in a command file, and if latencies are specified
that are long compared to the time required to collect a
frame of data, the fixed size of lats would be a problem.

In that case a better solution might be to use a dynamic
fifo approach for holding time values.

Both the main and latency_control processes end with a
wait statement.

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