"George Dishman" wrote in message
...

"ralph sansbury" wrote in message
...


I can understand the following:

Elsewhere you talk of a "sequence of voltages". If you stick
with that terminology which is entirely accurate, the
confusion won't arise.

.. The PLL locks on and tracks the carrier and it
uses a digital phase comparator that probably treats the
signal
as 1s and 0s.

It doesn't matter however for the
purposes of showing the essence of the procedure and the
rationale
as to why it is reliable.

Agreed.


The FFT finds the frequency with the highest amplitude, that
is correct. The computer then passes that measured frequency
to the PLL which is a completely separate system. It contains
a circuit that generates a known frequency and a phase
comparator. The phase comparator is described as "digital"
and probably uses only the polarity information, treating
the signal as 1 or 0 as you say. I was pointing out that it
is part of the PLL that does this, not the FFT.


I still dont understand what you mean by the multiplication
of voltages arriving at the two gates of dual gate transistor:
My sense of this is that the sum of the voltages produces a
pattern
which contains a frequency which is the difference frequency plus
the sum frequency plus the two input frequencies and that the
filters in the special circuits you refer to produce these
separate
components???.

This makes no sense. Electrical oscillations add by
the law of
superposition;

Yes, which is why it takes a special ciruit to get around
that.





All I can see is superposition and
then various filters to extract the desired frequency or
range of
frequencies